/*
 * =====================================================================================
 * Copyright (C) 2023 Ingenic Semiconductor Co.,Ltd
 * All Rights Reserved
 *
 * Filename     : reg_i2c.h
 * Author       : Keven <keven.ywhan@ingenic.com>
 * Created      : 2024/06/05 11:15
 * Description  :
 *
 * =====================================================================================
 */

#ifndef __REG_I2C_H__
#define __REG_I2C_H__

#include "reg_base.h"

#define I2C_CTRL            (0x00)    /*!< I2C control                               */
#define I2C_TAR             (0x04)    /*!< I2C target address                        */
#define I2C_SAR             (0x08)    /*!< I2C slave address                         */
#define I2C_HS_MADDR        (0x0C)    /*!< I2C HS Master Mode Code Address           */
#define I2C_DC              (0x10)    /*!< I2C data buffer and command               */
#define I2C_SHCNT           (0x14)    /*!< Standard speed I2C SCL high count         */
#define I2C_SLCNT           (0x18)    /*!< Standard speed I2C SCL low count          */
#define I2C_FHCNT           (0x1C)    /*!< Fast speed I2C SCL high count             */
#define I2C_FLCNT           (0x20)    /*!< Fast speed I2C SCL low count              */
#define I2C_HHCNT           (0x24)    /*!< High speed I2C SCL high count             */
#define I2C_HLCNT           (0x28)    /*!< High speed I2C SCL low count              */
#define I2C_INTST           (0x2C)    /*!< I2C Interrupt Status                      */
#define I2C_INTM            (0x30)    /*!< I2C Interrupt Mask                        */
#define I2C_RINTST          (0x34)    /*!< I2C Raw Interrupt Status                  */
#define I2C_RXTL            (0x38)    /*!< I2C RxFIFO Threshold                      */
#define I2C_TXTL            (0x3C)    /*!< I2C TxFIFO Threshold                      */
#define I2C_CINT            (0x40)    /*!< Clear Interrupts                          */
#define I2C_CRXUF           (0x44)    /*!< Clear RXUF Interrupt                      */
#define I2C_CRXOF           (0x48)    /*!< Clear RX_OVER Interrupt                   */
#define I2C_CTXOF           (0x4C)    /*!< Clear TX_OVER Interrupt                   */
#define I2C_CRXREQ          (0x50)    /*!< Clear RDREQ Interrupt                     */
#define I2C_CTXABRT          (0x54)    /*!< Clear TX_ABRT Interrupt                   */
#define I2C_CRXDN           (0x58)    /*!< Clear RX_DONE Interrupt                   */
#define I2C_CACT            (0x5C)    /*!< Clear ACTIVITY Interrupt                  */
#define I2C_CSTP            (0x60)    /*!< Clear STOP Interrupt                      */
#define I2C_CSTT            (0x64)    /*!< Clear START Interrupt                     */
#define I2C_CGC             (0x68)    /*!< Clear GEN_CALL Interrupt                  */
#define I2C_ENABLE          (0x6C)    /*!< I2C Enable                                */
#define I2C_ST              (0x70)    /*!< I2C Status register                       */
#define I2C_TXFLR           (0x74)    /*!< TxFIFO Level Register                     */
#define I2C_RXFLR           (0x78)    /*!< RxFIFO Level Register                     */
#define I2C_SDAHD           (0x7C)    /*!< I2C SDA Hold time Register                */
#define I2C_ABTSRC          (0x80)    /*!< I2C Transmit Abort Status Registe         */
#define I2CSDNACK           (0x84)    /*!< GenerateSLV_DATA_NACK Register            */
#define I2C_DMACR           (0x88)    /*!< DMA Control Register                      */
#define I2C_DMATDLR         (0x8C)    /*!< DMA Transmit Data Level                   */
#define I2C_DMARDLR         (0x90)    /*!< DMA Receive Data Level                    */
#define I2C_SDASU           (0x94)    /*!< I2C SDA Setup Register                    */
#define I2C_ACKGC           (0x98)    /*!< I2C ACK General Call Register             */
#define I2C_ENBST           (0x9C)    /*!< I2C Enable Status Register                */
#define I2C_FSPKLEN         (0xA0)    /*!< SS and FS Spike Suppression Limit         */

/* I2C Control Register (I2C_CTRL) */
#define I2C_CTRL_SLVDIS		(1 << 6)	/* after reset slave is disabled */
#define I2C_CTRL_REST		(1 << 5)
#define I2C_CTRL_MATP		(1 << 4)	/* 1: 10bit address 0: 7bit addressing */
#define I2C_CTRL_SATP		(1 << 3)	/* 1: 10bit address 0: 7bit address */
#define I2C_CTRL_SPDF		(2 << 1)	/* fast mode 400kbps */
#define I2C_CTRL_SPDS		(1 << 1)	/* standard mode 100kbps */
#define I2C_CTRL_MD		(1 << 0)	/* master enabled */

/* I2C Status Register (I2C_STA) */
#define I2C_STA_SLVACT		(1 << 6)	/* Slave FSM is not in IDLE state */
#define I2C_STA_MSTACT		(1 << 5)	/* Master FSM is not in IDLE state */
#define I2C_STA_RFF		(1 << 4)	/* RFIFO if full */
#define I2C_STA_RFNE		(1 << 3)	/* RFIFO is not empty */
#define I2C_STA_TFE		(1 << 2)	/* TFIFO is empty */
#define I2C_STA_TFNF		(1 << 1)	/* TFIFO is not full  */
#define I2C_STA_ACT		(1 << 0)	/* I2C Activity Status */

/* i2c interrupt status (I2C_INTST) */
#define I2C_INTST_IGC           (1 << 11)
#define I2C_INTST_ISTT          (1 << 10)
#define I2C_INTST_ISTP          (1 << 9)
#define I2C_INTST_IACT          (1 << 8)
#define I2C_INTST_RXDN          (1 << 7)
#define I2C_INTST_TXABT         (1 << 6)
#define I2C_INTST_RDREQ         (1 << 5)
#define I2C_INTST_TXEMP         (1 << 4)
#define I2C_INTST_TXOF          (1 << 3)
#define I2C_INTST_RXFL          (1 << 2)
#define I2C_INTST_RXOF          (1 << 1)
#define I2C_INTST_RXUF          (1 << 0)

/* i2c interrupt mask status (I2C_INTM) */
#define I2C_INTM_MIGC		(1 << 11)
#define I2C_INTM_MISTT		(1 << 10)
#define I2C_INTM_MISTP		(1 << 9)
#define I2C_INTM_MIACT		(1 << 8)
#define I2C_INTM_MRXDN		(1 << 7)
#define I2C_INTM_MTXABT		(1 << 6)
#define I2C_INTM_MRDREQ		(1 << 5)
#define I2C_INTM_MTXEMP		(1 << 4)
#define I2C_INTM_MTXOF		(1 << 3)
#define I2C_INTM_MRXFL		(1 << 2)
#define I2C_INTM_MRXOF		(1 << 1)
#define I2C_INTM_MRXUF		(1 << 0)

#define I2C_DC_REST		(1 << 10)
#define I2C_DC_STP		(1 << 9)
#define I2C_DC_READ    		(1 << 8)

#define I2C_ENB_I2CENB		(1 << 0)	/* Enable the i2c */

#define I2C_FIFO_LEN		(64)

#define TX_LEVEL		(I2C_FIFO_LEN / 2)
#define RX_LEVEL		(I2C_FIFO_LEN / 2 - 1)

/* I2C standard mode high count register(I2CSHCNT) */
#define I2CSHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
/* I2C standard mode low count register(I2CSLCNT) */
#define I2CSLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))
/* I2C fast mode high count register(I2CFHCNT) */
#define I2CFHCNT_ADJUST(n)      (((n) - 8) < 6 ? 6 : ((n) - 8))
/* I2C fast mode low count register(I2CFLCNT) */
#define I2CFLCNT_ADJUST(n)      (((n) - 1) < 8 ? 8 : ((n) - 1))

enum {
	I2C_STATE_READY,
	I2C_STATE_BUSY_TX,
	I2C_STATE_BUSY_RX,
	I2C_STATE_BUSY_DMA_TX,
	I2C_STATE_BUSY_DMA_RX,
};


#endif /* __REG_I2C_H__ */
